TetraPower 970MP (CANCELED) Project
Critical Design Review of Schematicsin category Hardware
proposed by bboettjer on 3rd March 2006
Project Proposal
Having experience with five mature 970 hardware designs (in production), there exists a (long) short-list of issues in hardware that keep coming up. We have developed over 400 pages of \'rules\' that the router must adhere to for any 970 design.Voltage translation buffers for I2C, I2C tree topology, philips I2C part quirkiness, CPC925/970 I2C non-compliance issues and 970 \'leakiness\' mandating that each processor and bridge be separated from each other in the I2C tree are amongst the electrical issues...
CPC925/35/45 errata issues must be known and designed around.
Careful power plane management is a requirement in order to ensure that all of the interfaces come up without noise.
CPC925/35/45 requires a non-standard pad size in order to reliably/repeatedly be able to manufacture the chip onto the board. Layer stack-up, copper concentration and line lengths are CRITICAL in achieving a working design (on all of my designs I matched ALL of the EI lengths to within 5 10,000ths of an inch)... it may sound aggressive, but it was what experience taught us will work.
970 pads require \'dog-bones\' to the vias on power pins in order to reduce di/dt issues...
etc... the list goes on.
It would frankly be amazing to see a 970 design come up at all without some/all of these considerations getting taken into account.
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