TetraPower 970MP (CANCELED) Project
Memory Bus Tuningin category Hardware
proposed by bboettjer on 1st March 2006
Project Proposal
The memory bus on the NorthBridge has delay elements built into each IO. These delay elements are controlled on a per byte basis.Finding the range of valid delay-element values, where a specific byte lane will operate correctly for a given speed is very non-trivial.
The speed of the NorthBridge (a yeild parameter) is also taken into account, as this has a direct impact on how fast each delay element is.
Finding the center of the possible range of values, for each byte lane, for each group of signals (Clock, control & data) is very difficult and requires a significant amount of software for tuning runs as well as high speed scopes to capture traces in order to evaluate which way to make a specific signal walk.
The resulting parameters accompany a specific lot of northbridges throughout the life of the board. Lookup space must be provided in the service processor to fetch different values based on die speed.
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