After some blood, sweat and tears were put into it (Christmas break notwithstanding) and a lot of cutting down example code meant for cards with PCI Master cores available (like the Cyclone II), I finally got a working PCI target control state machine running.

Now, we have a MAXII PCI board in an Efika (with a 90-degree riser and a modified Open Client case so that the board is exposed) which implements a very simple, student-understandable PCI concept - i.e. it's simple, concise and is written in VHDL rather than Verilog. Right now, all you can do is read and write some LED status, and check the status of 4 pushbutton switches, but these are exposed through a Linux kernel driver and a /proc filesystem interface such that they can be read by userspace.

The next step is to enable a more advanced peripheral such as the onboard VFD LCD controller, which will allow some text output from designs (or be controlled from the driver/proc interface). This requires a more complex state machine which can handle PCI retries and insert wait states, since the bus on the VFD controller is far, far slower than the PCI clock. There is also some cleanup and documentation in the VHDL core to be done, to make sure the entire thing is as transparent as possible.

I think we will put the code up on the web for everyone to see in the very near future.