We decided to take a region-based approach for the vector graphics; the PowerPC will render each vector graphics element into a (framebuffer) region in local SDRAM, which is then DMA transferred to the FPGA SDRAM as a rectangle region (RGBA).

The FPGA appears as a local bus memory device.

The common datastructure is a look-up table containing all regions. For each video pixel, at most one region can overlap. During the video scan, for each pixel, the FPGA does a lookup, calculates the memory address and alpha-blends the pixel values from video and graphics.

Using the FPGA SDRAM controller, we found that each region may not be smaller than 8 pixels in order to still have enough bandwidth in the worst-case layout (where a horizontal video line is fully occupied with regions)