On PPCNUX is a very interesting to read article about the new POWER-6 CPU. http://www.ppcnux.de/?q=node/7138 (in german)
The article is partly based on this IBM note: http://www.research.ibm.com/journal/rd/516/le.html

I like the article on PPCnux. It nicely describes the features of the POWER6 CPU. ONe thing is clear, the Power6 is propably the most powerfull CPU as of today.

But I think that you always need to read those article and numbers with a grain of salt. ;-)
PPCNUX counts that the POWER6 does have a memory bandwidth of 50 GB/sec for reads and 25 GB/sec for memory writes.
PPCNUX compares this with the max bandwith of the CELL of 25 GB/sec and with the Xeon having 12 GB/sec.

Its obvious that these numbers are theoretical values and that the real world performance of these CPUs is different.

We have at work some Xeon and Opteron servers. Despite using MMX and SSE optimized memcopy routines I could never got over 3GB thoughput out of their x86 cores.

And while its true that the CELL has a max bandwidth of 25 GB/sec but was not possible to get over 5 GB/sec out of it PPC core on my PS3. But if you use the DMA on a few of the CELL-SPE then you can utilize the full bandwidth.
So the CELL PPC core is beating the Opteron and Xeon hands down in this test. ;-)

While theoretical numbers are nice to read, I find real world numbers much more valuable to judge the performance. :-)
For the x86 family I saw that 3GB was still the limit for least years DELL server generation.
For the CELL PPC, 4.5 GB is the maximum that I could get out of it.
For my G5 I know that it reaches 4 GB/sec. Its interesting to see that the G5 still was able to beat newer x86 chips. ;-)
And Arno did quote here the Freescale benchmarks. Sergei of Freescale did 3GB/sec with the Dual G4 Chip. Sergei said it will be 4GB using faster mem-modules.


I wonder if someone will be able to reach 8 GB/sec of real world performance on the POWER6.


Does anyonw have real world numbers for POWER5 or POWER6 ?

Cheers
Gunnar

And if you read the IBM article on the subject, you'll see that what has those capacities are the peak numbers for the bus between the memory controller and the memory modules:

"While the interface between the POWER6 chip and the buffer chips supports 51.2 GB/s of peak read bandwidth and 25.6 GB/s of peak write bandwidth when using 800-MHz DDR2 DRAM with both memory controllers driving four channels each, the sustainable bandwidth is dependent upon the number of daisy-chained buffer chips per channel and the number of DRAM chips multidropped to each buffer chip, as well as the read and write traffic pattern."

Keep in mind that the ibm server chips are made with the intention of making well-balanced designs for very large SMP systems. In other words, you could have several (many) cpus accessing memory through the same controllers, etc.

Hi Gunnar,

ojn is right, the quoted Power6 figures are theoretical maximum for DDR2-800 with 8 channels.

The new JS22 Power6 blade uses just 2 channels for each chip, so we are looking at a 21 GB/s maximum.

IBM released a STREAM benchmark result of just under 16 GB/s, so here you have your 8 GB/s per chip. ;-)

AMD is a great performer, too.