Hello,
from the SFW bootup output, it seems core clock is 396 and at least XPB clock seems to be 132 MHz (based on MPC5200B user manual) The question is: is IPB clock 132 or 66 MHz?
Thanks,
Karel

Why do you need to know that? :)

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Matt Sealey

Because in current generic 5200 BSP, it's needed to configure those three clocks. For example following comments in code, IPB clock is the same as in Bestcomm and Bestcomm clock is what you need to know to configure serial port bauds correctly.

Thanks,
Karel

So it seems it's 66 MHz if anyone also needs this.
Karel

If you're coding in Linux using the platform support provided by 2.6.20 onwards, you can use the function;
I got that from the serial port driver. You should pass in the node of the device you're using, which should probably be a child node of /builtin for it to work.

Essentially, the value is the 'bus-frequency' property of the /builtin node.

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Matt Sealey

Hello,
that's interesting observation. Anyway, I'm not sure if it's correct, since returned 'bus-frequency' is 132MHz. The problem is that the driver author a few lines below divide it twice and use it as an 'uart' frequency. See: It's interesting since if I understand mpc5200b user's manual well, then uart clock is exactly the same like bestcomm clock which is again the same like IPB clock. (Paragraph 5.3.5 IPB Clock Domain). So If I'm right Linux folks just get XLB clock frequency and assume that IPB = XLB /2, which don't need to be true (Tables 5-4 and 5-5).

Please correct me if I'm wrong.

Thanks!
Karel

The way I understand it, the XLB runs at a certain clock, and the IPB runs at a derivative and divided clock (same or half) of the XLB, and the PCI bus runs at yet another derivative clock of the IPB (same or 2 or 4).

If the XLB runs at 132MHz, the IPB can run at 132MHz, 66MHz or 33MHz. The PCI bus runs at the same or half or a quarter of the IPB but has to be 66MHz or 33MHz (to fit spec) and no more than the IPB.

As far as I understand, Efika's XLB is 132MHz, the IPB is 132MHz (no divider), and the PCI bus is 66MHz (2x divider).

I'm not sure why the UART driver divides the IPB by 2 - but it is storing 'uartclk' and not 'ipbclock' in that structure. I have to read a chapter of the manual and check the code to work it out (15.3.1.2) to see what prescalers and dividers it's using in the clock generation.

If the division by 2 was merely to get the correct IPB frequency from a misreporting device tree, then the UART driver would be broken on Lite5200, so I don't think you're correct :)

It may be just simpler to deal with the value by dividing it there. If you are really concerned of the real values, read the CDM configuration register (mbar + 0x20c) and check your values.

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Matt Sealey