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Two new papers about DSP on AltiVec
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Author:  Krashan [ Mon Oct 02, 2006 1:32 am ]
Post subject:  Two new papers about DSP on AltiVec

My two new scientific papers about optimizing FIR filters on AltiVec has been published. Both of them are about optimizing long FIR-s operating on long (or unlimited) streams of [audio] data. The first one, titled "Fast FIR Filters for SIMD Processors With Limited Memory Bandwidth" (PDF) has been published on XI Symposium AES "New Trends in Audio and Video" in Bialystok, describes floating point filters, while the second one, "Performance Analysis of Alternative Structures for 16-bit Integer FIR Filter Implemented on AltiVec SIMD Processing Unit" (PDF) published on IEEE Workshop of Signal Processing in Poznan, concentrates on 16-bit integer filters. There is also a seminar presentation of the second one. References to the source code and benchmarks are placed inside papers. For long filters (1000 taps or more) I've achieved 2.5 Gtaps per second for floating point filter and 6.5 Gtaps per second for integer filter. All this on 1.0 GHz 7447 unit and Pegasos II. Presented ideas are implemented in a class of Reggae multimedia framework for MorphOS.

Author:  bbrv [ Mon Oct 02, 2006 6:16 am ]
Post subject: 

That is great Krashan. 8)

We will check it out!

R&B :)

Author:  markos [ Tue Oct 03, 2006 1:09 pm ]
Post subject:  Re: Two new papers about DSP on AltiVec

Quote:
My two new scientific papers about optimizing FIR filters on AltiVec has been published. Both of them are about optimizing long FIR-s operating on long (or unlimited) streams of [audio] data. The first one, titled "Fast FIR Filters for SIMD Processors With Limited Memory Bandwidth" (PDF) has been published on XI Symposium AES "New Trends in Audio and Video" in Bialystok, describes floating point filters, while the second one, "Performance Analysis of Alternative Structures for 16-bit Integer FIR Filter Implemented on AltiVec SIMD Processing Unit" (PDF) published on IEEE Workshop of Signal Processing in Poznan, concentrates on 16-bit integer filters. There is also a seminar presentation of the second one. References to the source code and benchmarks are placed inside papers. For long filters (1000 taps or more) I've achieved 2.5 Gtaps per second for floating point filter and 6.5 Gtaps per second for integer filter. All this on 1.0 GHz 7447 unit and Pegasos II. Presented ideas are implemented in a class of Reggae multimedia framework for MorphOS.
Krashan,
These are excellent papers and the results are astonishing!!! I am very interested to study the source code in detail, as soon as I'm "free" again (a few more days, just a few :-D) from my military service!

What I find very intriguing is the possibility that these algorithms may be applied to image processing applications as well, like GIMP, in particular the digital convolution filters, which I believe work in the same or similar way. Esp, since your code applies to "real" data -ie big data and not just "Proof of Concept" lab tests.

Keep them coming!

Konstantinos

Author:  bbrv [ Wed Oct 04, 2006 12:55 am ]
Post subject: 

@markos

In Krashan, we think we found an agile development partner for you. After all, look at his Pegasos:

http://www.chal.republika.pl/album/slides/PICT3587.html

Take another look:

http://www.chal.republika.pl/album/slides/PICT3588.html
http://www.chal.republika.pl/album/slides/PICT3590.html

R&B :)

Author:  Grzegorz Kraszewski [ Wed Oct 04, 2006 2:07 am ]
Post subject:  Re: Two new papers about DSP on AltiVec

Quote:
What I find very intriguing is the possibility that these algorithms may be applied to image processing applications as well, like GIMP, in particular the digital convolution filters, which I believe work in the same or similar way. Esp, since your code applies to "real" data -ie big data and not just "Proof of Concept" lab tests.
Of course the principle of reducing memory accesses and paralellizing computations is valid for 2D convolutions. It will be the next step and results will be published in my Ph. D. dissertation which is about optimizing DSP algorithms for SIMD units placed in systems with limited memory bandwidth.

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